1. Field of the Invention
The present invention relates to bridge circuits for managing data flow between components of a computer system. More specifically, the present invention relates to a bridge circuit that incorporates a bi-directional buffering system to control address and data transfers between a processor and components attached to a computer bus.
2. Description of the Related Art
Most currently available computer systems include several substructures including a central processing unit ("CPU" or "processor"), a memory architecture, and an input/output (I/O) system. As is well known, the processor processes information that is provided to it by other substructures in the computer system. The memory substructure acts as a storage area for holding commands and data that are eventually acted upon by the processor or other computer components. The input/output system of the computer provides an interface for the computer system to communicate with peripheral devices such as hard disks, monitors and telephone modems. Within the computer are several "buses" that manage communications and data transfers between the various computer substructures. For example, a host bus manages information flow to and from the processor. Accordingly, data and address information moving to and from the processor travels across the processor bus. In addition an I/O bus manages communications between peripheral devices and other parts of the computer system.
As faster processors and peripherals have become available to computer manufacturers, the importance of efficiently transferring address and data information between computer substructures has increased. For example, the I/O bus in early personal computers transferred data at a speed of 8 MHz whereas the I/O bus in modern personal computers runs at 33 MHz.
One factor that has driven the development of more efficient mechanisms for transferring information across the I/O bus is the ever-increasing speed of modern processors. Unfortunately, technology relating to bus substructures has not advanced at the same rate as the technology relating to processors. For example, processors in modern personal computer systems can run at speeds which may be double or triple the speed of the I/O bus. This is mostly due to the inherent difficulty of transferring data through the numerous connectors that allow peripheral devices to communicate with the computer system. Computer system designers have found that communication errors arise when peripheral devices are connected at high bus speeds through many connectors and bridges.
As an example, current Intel.RTM. Pentium.RTM. Pro-based personal computers have a 200 MHz processor bus and a 33 MHz Peripheral Component Interconnect (PCI) I/O bus. Due to the speed differential between the Pentium.RTM. Pro processor bus and the PCI bus, the Pentium.RTM. Pro processor is forced, in many instances, to wait through several clock cycles before accessing the PCI bus to send address or data information to a peripheral device.
To circumvent this problem, others have placed First In/First Out (FIFO) buffers between the Pentium.RTM. processor bus and the PCI bus. For example, the Intel.RTM. 82433LX Local Bus Accelerator Chip includes a four double word deep processor-to-PCI posted write buffer for buffering data writes from the Pentium.RTM. processor to peripheral devices on the PCI bus. This buffer is a simple first-in/first-out (FIFO) buffer wherein the destination address is stored in the buffer with each double word of data. In use, the processor-to-PCI posted write buffer is positioned within a bridge circuit, between the processor bus and the PCI bus. As the processor generates data writes to the PCI bus, the data is queued in the posted write FIFO buffer of the Intel.RTM. 82433LX.
The FIFO buffered bridge structure of the Intel.RTM. 82433LX allows the Pentium.RTM. Pro Processor to complete processor to PCI double word memory writes in three processor clocks (with one wait-state), even if the PCI bus is busy on the first clock. Once the PCI bus becomes available, the posted write data stored in the FIFO buffer is written to the designated PCI device. Uncoupling the processor request from the PCI bus in this manner allows the processor to continue processing instructions while waiting to retrieve the designated information from the PCI bus.
In addition to the four double word deep posted write buffer, the Intel.RTM. 82433LX also includes a processor-to-PCI read pre-fetch buffer. The pre-fetch buffer is four double words deep and enables faster sequential Pentium.RTM. Pro Processor reads from the PCI bus. The Intel.RTM. 82433LX read pre-fetch buffer is organized as a simple FIFO buffer that only supports sequential reads from the PCI bus.
In practice, data is sent from the PCI bus, through the processor-to-PCI read pre-fetch buffer, to the processor. Processors such as the Intel.RTM. Pentium.RTM. Pro include an instruction pre-fetch circuit so they can gather instructions that are about to be executed by the processor.
Unfortunately, attempts at solving the problem of processors running faster than bus substructures have not met with complete success. Many Intel.RTM. Pentium.RTM. Pro-based computer systems that employ FIFO buffering schemes to manage data traffic between the PCI bus and the processor are still inserting one or more wait states into their bus read and write instructions. This lowers the computer system's performance and causes many software programs to run slower than necessary.
As one example, the Intel.RTM. 82433LX only provides a limited flexibility for handling data writes and reads to the PCI bus. In particular, the processor-to-PCI posted write buffer and processor-to-PCI read pre-fetch buffer are both unidirectional FIFOs and therefore do not allow for random access of their contents. Moreover, if the processor is performing a tremendous number of write instructions to the PCI bus, the posted write buffer does not have the flexibility to handle more than four double words. Thus, wait states are inserted into the processor clock until the FIFO buffers are cleared. For all of the above reasons, it would be advantageous to provide a system that had the flexibility to allow additional buffers to become available during peak write and read periods. This flexibility is offered by the system of the present invention.